PRODUCT

OP-FW12GA Firmware for High-speed Communication

Outline

OP-FW12GA is the firmware to increase the speed of monitoring test of bit synchronous communication (such as HDLC/SDLC/X.25, or CC-Link communication), SPI communication, Profibus-DP (field bus known for high-speed communication), UART (asynchronous communication, which is commonly used). By processing great part of  monitoring processes by FPGA, it unfailingly captures communication data with time stamps of a microsecond rate. The interface supports RS-232C/RS-422/RS-485/TTL.

Firmware OP-FW12G
Version 2.00 or later
OP-FW12GA
UART No Yes
HDLC Yes Yes
SPI Yes Yes
Profibus-DP No Yes

Operating Instructions

RS-232C
Connect to RS-232C port of analyzer using the monitor cable “LE-25M1”.

RS-422/485
Connect to RS-422/485 line as shown in the following figure by using the terminal block for DSUB 25-pin (LE-25TB) etc. of an option.
Half-duplex 2 (TxD_A), 14 (TxD_B)
7 Connect (GND)
Full-duplex 2 (TxD_A), 14 (TxD_B)
3 (RxD_A), 16 (RxD_B)
7 Connect (GND)

If you need the terminator, turn on by DIP SW on the interface board.



TTL
Connect using the optional expansion kit “OP-SB85/OP-SB85L”.

<HDLC Monitor>
<HDLC Simulation>
<SPI Monitor>

<SPI Simulation>
 
 * Master Mode
  Connect SDO(SD) to MOSI, SDI(RD) to MISO,
  SS(RTS) to SS, and SCK(TXC) to SCK.
  

 *Slave Mode
  Connect SDO(SD) to MOSI, SDI(RD) to MISO,
  SS(RTS) to SS, and SCK(TXC) to SCK.
  

Monitoring

It can monitor ASYNC/HDLC/Profibus-DP (Max 12Mbps) or SPI (Max 20Mbps) at arbitrary speed in real-time. Time stamp resolution that is effective to check the response time is selectable from 1mS/100uS/10uS/1uS. Therefore, it is useful for development and analysis of failures for High-speed communications effectively.

ASYNC
<ASYNC Setup Screen>

ASYNC monitor function supports data bit length (7 or 8 bit), parity bit (none, even, or odd), and BCC (LRC-ODD/LRC-EVEN/CRC-16/CRC-ITU-T). With OP-SB85L, it can easily measure UART of microcomputer or communication module.

HDLC/SDLC/X.25 and CC-Link

ID filter that can capture frames only on the specific address (16bits) can be individually specified on the SD and RD side. This improves the efficiency of analysis and data use in the capture memory. At the time of the half-duplex, the frames of specific address can be divided to the SD side, the other frames are sent to the RD side.

<HDLC Setup Screen>
<HDLC Monitoring Screen>(normal)
<HDLC Monitoring Screen>(frames)
<HDLC Monitoring Screen>(packets)
SPI
There are 4 kinds of SPI transferring timing by clock polarity and clock phase.This products supports all these kinds and monitors SPI communications in most of the SPI devices. Some of the SPI devices transer all frames with low level SS signal. This product can analyze the relationship between transferring commands and data by setting the Frame End Time. <SPI Setup Screen>
<SPI Monitoring Screen>(normal)
<SPI Monitoring Screen>(dump)
Profibus-DP
It supports Profibus-DP (A high-speed fieldbus prevailing in the world). It takes frames out according to the communication standard of Profibus and you can see it in the translated display or execute error check of BCC. <Profibus Monitoring Screen>(normal)
<Profibus Monitoring Screen>(translate)
<Profibus Monitoring Screen>(dump)

Trigger

<Example of Trigger Setup Screen1>
<Example of Trigger Setup Screen2>
<Example of Trigger Setup Screen3>
It outputs a Low pulse to the external trigger terminal or automatically stops monitoring by single detection or sequential detection of two sets of characters (max 8 characters, you can choose don’t care and bit mask) or by detection of an error (CRC error, abort, short frame).

Simulation

<SPI Setup Screen>

Simulation function is useful when it is in the early stage of development, and when there are few partner devices to perform high-speed communications. By pressing the corresponded key, 16 kinds of data registered in the transmission data table can be transmitted once or repeatedly. For TTL interface, you can select the output signal level and type that suits to the target circuit. For SPI simulation, it has Master and Slave mode, and able to have the transmission/reception test up to 12Mbps (Master mode).

Support Logic Analyzer function

Logic Analyzer function at max 100MHz sampling speed enables you to analyze timing of high-speed HDLC and SPI signals by digital waveform. It helps you to solve the hardware troubles, and it is also useful for educational purpose for data communication studies.

When the analyzer is LE-8200A, you can use pulse generator function with which you can edit and output a waveform.

Specification

Interface RS-422/RS-485(RS-530)*1, TTL*2, SPI*2
Protocol HDLC, SDLC, X.25, CC-Link(NRZ/NRZI format, AR clock*3), SPI, ASYNC, Profibus
Speed HDLC, CC-Link
ASYNC
Profibus
115.2kbps - Full-duplex 6Mbps / Half-duplex 12Mbps*4
SPI 115.2kbps - 20Mbps*4*5
Max 12Mbps (master mode) / 6Mbps (slave mode) when using simulation mode.
Setting steps User-set: 4 effective digits
Error Check FCS Error(CRC-ITU-T), Abort, short frame, Brake, Framing error, Parity error, BCC error
On-line Monitor Time stamps 9 digits , 0 to 134217727
selectable in 1mS, 100μS, 10μS or 1μS
ID Filter (HDLC) able to set 2 characters (don't care, bit masks available)
Simulation Transmission
data table
16K data (can be divided to 160 tables)
MANUAL mode Data table corresponding to the numerical keys can be sent
Able to set continuous transmission and interval.
Trigger It outputs a Low pulse of 1μs to the external trigger terminal or automatically stops monitoring by single detection or sequential detection of two sets of characters (max 8 characters, you can choose don’t care and bit mask) or by detection of an error (CRC error, abort, short frame).
Logic analyzer function clock 1KHz-40MHz, 100MHz
memory 4000 sampling
PULSGEN function*6 It regenerates the timing waveform on a communication line, which captured by the logic analyzer function.
Data Search search any trigger data, error data and character lines
Auto Run/Stop Measurement starts and stops in appointed time
Composition Firmware CD, Instruction Manual
*1 when using the standard board
*2 necessary to have OP-SB85/OP-SB85L.
*3 The synchronous clock extracted from the edge of the transmission and reception data.
*4 necessary to have OP-SB85L for high-speed simulation of TTL/SPI.
*5 when transmission data continues more than 16byte, max speed may be at max. 6Mbps.
*6 This function requires LE-8200A.