OP-FW12G Firmware for High-speed HDLC/SPI communications (NEW Version)


This expansion firmware increases the baud rates of bit synchronous communications (e.g., HDLC/SDLC/X.25, and CC-Link communications). The firmware processes main measurement items completely with a field programmable gate array (FPGA), thus precisely capturing communications data along with time stamps in 1-µs units.

*From version 2.00(or later), it supports TTL signal level of HDLC/SPI communications measured by LE-8200 with TTL expansion kit “OP-SB85/OP-SB85L”.

Operating Instructions

Connect to RS-232C port of analyzer using the monitor cable “LE-25M1”.

Connect to RS-422/485 line as shown in the following figure by using the terminal block for DSUB 25-pin (LE-25TB) etc. of an option.
Half-duplex 2 (TxD_A), 14 (TxD_B)
7 Connect (GND)
Full-duplex 2 (TxD_A), 14 (TxD_B)
3 (RxD_A), 16 (RxD_B)
7 Connect (GND)

If you need the terminator, turn on by DIP SW on the interface board.

Connect using the optional expansion kit “OP-SB85/OP-SB85L”.

<HDLC Monitor>
<HDLC Simulation>
<SPI Monitor>

<SPI Simulation>
 * Master Mode
  Connect SDO(SD) to MOSI, SDI(RD) to MISO,
  SS(RTS) to SS, and SCK(TXC) to SCK.

 *Slave Mode
  Connect SDO(SD) to MOSI, SDI(RD) to MISO,
  SS(RTS) to SS, and SCK(TXC) to SCK.


It is able to monitor HDLC communications at arbitrary speed up to 12Mbps (20Mbps for SPI communications). Time stamp resolution that is effective to check the response time is selectable from 1mS/100uS/10uS/1uS. Therefore, it is useful for development and analysis of failures for High-speed communications effectively.
HDLC/SDLC/X.25 and CC-Link
<HDLC Setup Screen>
ID filter that can capture frames only on the specific address (16bits) can be individually specified on the SD and RD side. This improves the efficiency of analysis and data use in the capture memory. At the time of the half-duplex, the frames of specific address can be divided to the SD side, the other frames are sent to the RD side.
<HDLC Monitoring Screen>(normal)
<HDLC Monitoring Screen>(packets)
<SPI Setup Screen>
There are 4 kinds of SPI transferring timing by clock polarity and clock phase.This products supports all these kinds and monitors SPI communications in most of the SPI devices. Some of the SPI devices transer all frames with low level SS signal. This product can analyze the relationship between transferring commands and data by setting the Frame End Time.
<SPI Monitoring Screen>(normal)
<SPI Monitoring Screen>(dump)


<Example of Trigger Setup Screen1>
<Example of Trigger Setup Screen2>
<Example of Trigger Setup Screen3>
When 2 sets of communication data string up to 8 characters (don’t care and bit mask available) is detected individually or sequentially, or when error (CRC error, abort, short frame) is detected, monitoring action can be stopped automatically.


<SPI Setup Screen>
Simulation function is useful when it is in the early stage of development, and when there are few partner devices to perform high-speed communications. By pressing the corresponded key, 16 kinds of data registered in the transmission data table can be transmitted once or repeatedly. For TTL interface, you can select the output signal level and type that suits to the target circuit. For SPI simulation, it has Master and Slave mode, and able to have the transmission/reception test up to 12Mbps (Master mode).

Support Logic Analyzer function [Ver.2.03]

Logic Analyzer function at max 100MHz sampling speed enables you to analyze timing of high-speed HDLC and SPI signals by digital waveform. It helps you to solve the hardware troubles, and it is also useful for educational purpose for data communication studies.


Interface S-422/485 (RS-530)*1, TTL*2, SPI*2
Protocol HDLC, SDLC, X.25, CC-Link(NRZ/NRZI format, AR clock*3), SPI
Speed HDLC, CC-Link 115.2kbps - Full-duplex 6Mbps / Half-duplex 12Mbps*4
SPI 115.2kbps-20Mbps*4*5 Max12Mbps for simulation
Setting steps User-set: 4 effective digits
Error Check FCS Error(CRC-ITU-T), Abort, short frame
On-line Monitor Time stamps 9 digits , 0 to 134217727
selectable in 1mS, 100μS, 10μS or 1μS
ID Filter (HDLC) able to set 2 characters (don't care, bit masks available)
Simulation Transmission
data table
16K data (can be divided to 16 tables)
MANUAL mode Data table corresponding to the numerical keys can be sent
Able to set continuous transmission and interval.
Trigger Set up to 8 characters (don't care and bit masks available).
When 2 individual or sequential characters, errors or the external trigger input(low level) are found, the analyzer automatically stops monitoring.
Data Search search any trigger data, error data and character lines
Auto Run/Stop Measurement starts and stops in appointed time
Composition Firmware CD, Instruction Manual
*1 when using the standard board
*2 necessary to have OP-SB85/OP-SB85L.
*3 The synchronous clock extracted from the edge of the transmission and reception data.
*4 necessary to have OP-SB85L for high-speed simulation of TTL/SPI.
*5 when transmission data continues more than 16byte, max speed may be at max. 6Mbps.