Firmware Version History for OP-FW12G

Add Logic Analyzer (Wave monitor) function at max 100MHz sampling speed.
Support Bit sequence at LSB First (SPI protocol) when using TTL/I2C/SPI expansion board (OP-SB85L/OP-SB85L).
Able to transmit data when Clock phase is “0” without SS signal at SPI simulation.
Set back the SDO signal to be “1” when there is a rising edge of SS signal or another clock after transmission of the last bit at SPI Slave simulation.

Correct bug of wrong position of active status for external trigger signal when using standard board.
Correct bug that analyzer cannot measure HDLC communications when starting flag is also used as ending flag.
Correct bug that HDLC short frame is recognized as normal frame.
Correct bug of invalid trigger function when starting flag is set as trigger condition.
Correct bug of capturing loss when there is difference on speed between transmission and reception.
LINEEYE warrants that analyzer can measure communications if the difference on speed is within 40%.

Correct the bug of mis-counting the date of timestamp when measuring data for a couple months.
(Timestamp will be incorrect when measuring into another month.) Timestamp will be correct when turning off the analyzer.
Correct the bug of auto-saving. When there is not enough capacity in the CF card, there will be some corrupt auto-saving files and become error. It will not happen when specifying the size and numbers of auto-saving file within the capacity of the CF card.
Correct the guide message in English, "1:Stop" is changed to "1:Count" at "Action" of the Data Retrieval function.

Support TTL signal level of HDLC/SPI communications (when using with OP-SB85/OP-SB85L)
Improve the capability of measuring SPI communications.
Improve the ways of accessing to the CF card file.
Correct the miner bug of remote control.